CWE-1264: Hardware Logic with Insecure De-Synchronization between Control and Data Channels

Description

The hardware logic for error handling and security checks can incorrectly forward data before the security check is complete.

Many high-performance on-chip bus protocols and processor data-paths employ separate channels for control and data to increase parallelism and maximize throughput. Bugs in the hardware logic that handle errors and security checks can make it possible for data to be forwarded before the completion of the security checks. If the data can propagate to a location in the hardware observable to an attacker, loss of data confidentiality can occur. 'Meltdown' is a concrete example of how de-synchronization between data and permissions checking logic can violate confidentiality requirements. Data loaded from a page marked as privileged was returned to the CPU regardless of current privilege level for performance reasons. The assumption was that the CPU could later remove all traces of this data during the handling of the illegal memory access exception, but this assumption was proven false as traces of the secret data were not removed from the microarchitectural state.

Potential Impact

Confidentiality

Read Memory, Read Application Data

Demonstrative Examples

There are several standard on-chip bus protocols used in modern SoCs to allow communication between components. There are a wide variety of commercially available hardware IP implementing the interconnect logic for these protocols. A bus connects components which initiate/request communications such as processors and DMA controllers (bus masters) with peripherals which respond to requests. In a typical system, the privilege level or security designation of the bus master along with the intended functionality of each peripheral determine the security policy specifying which specific bus masters can access specific peripherals.  This security policy (commonly referred to as a bus firewall) can be enforced using separate IP/logic from the actual interconnect responsible for the data routing.

Bad

The firewall and data routing logic becomes de-synchronized due to a hardware logic bug allowing components that should not be allowed to communicate to share data. For example, consider an SoC with two processors. One is being used as a root of trust and can access a cryptographic key storage peripheral. The other processor (application cpu) may run potentially untrusted code and should not access the key store. If the application cpu can issue a read request to the key store which is not blocked due to de-synchronization of data routing and the bus firewall, disclosure of cryptographic keys is possible.

Good

All data is correctly buffered inside the interconnect until the firewall has determined that the endpoint is allowed to receive the data.

Mitigations & Prevention

Architecture and Design

Thoroughly verify the data routing logic to ensure that any error handling or security checks effectively block illegal dataflows.

Real-World CVE Examples

CVE ID	Description
CVE-2017-5754	Systems with microprocessors utilizing speculative execution and indirect branch prediction may allow unauthorized disclosure of information to an attacker with local user access via a side-channel an

Frequently Asked Questions

What is CWE-1264?

CWE-1264 (Hardware Logic with Insecure De-Synchronization between Control and Data Channels) is a software weakness identified by MITRE's Common Weakness Enumeration. It is classified as a Base-level weakness. The hardware logic for error handling and security checks can incorrectly forward data before the security check is complete.

How can CWE-1264 be exploited?

Attackers can exploit CWE-1264 (Hardware Logic with Insecure De-Synchronization between Control and Data Channels) to read memory, read application data. This weakness is typically introduced during the Architecture and Design, Implementation phase of software development.

How do I prevent CWE-1264?

Key mitigations include: Thoroughly verify the data routing logic to ensure that any error handling or security checks effectively block illegal dataflows.

What is the severity of CWE-1264?

CWE-1264 is classified as a Base-level weakness (Medium abstraction). It has been observed in 1 real-world CVEs.