CWE-1298: Hardware Logic Contains Race Conditions

Description

A race condition in the hardware logic results in undermining security guarantees of the system.

A race condition in logic circuits typically occurs when a logic gate gets inputs from signals that have traversed different paths while originating from the same source. Such inputs to the gate can change at slightly different times in response to a change in the source signal. This results in a timing error or a glitch (temporary or permanent) that causes the output to change to an unwanted state before settling back to the desired state. If such timing errors occur in access control logic or finite state machines that are implemented in security sensitive flows, an attacker might exploit them to circumvent existing protections.

Potential Impact

Access Control

Bypass Protection Mechanism, Gain Privileges or Assume Identity, Alter Execution Logic

Demonstrative Examples

The code below shows a 2x1 multiplexor using logic gates. Though the code shown below results in the minimum gate solution, it is disjoint and causes glitches.

Bad

// 2x1 Multiplexor using logic-gates
                        
						module glitchEx(
						
							input wire in0, in1, sel,
							output wire z
						
						);
                        
						wire not_sel;
						wire and_out1, and_out2;
						
						assign not_sel = ~sel;
						assign and_out1 = not_sel & in0;
						assign and_out2 = sel & in1;
                        
						// Buggy line of code:
						assign z = and_out1 | and_out2; // glitch in signal z
						
						endmodule

The buggy line of code, commented above, results in signal 'z' periodically changing to an unwanted state. Thus, any logic that references signal 'z' may access it at a time when it is in this unwanted state. This line should be replaced with the line shown below in the Good Code Snippet which results in signal 'z' remaining in a continuous, known, state. Reference for the above code, along with waveforms for simulation can be found in the references below.

Good

assign z <= and_out1 or and_out2 or (in0 and in1);

This line of code removes the glitch in signal z.

The example code is taken from the DMA (Direct Memory Access) module of the buggy OpenPiton SoC of HACK@DAC'21. The DMA contains a finite-state machine (FSM) for accessing the permissions using the physical memory protection (PMP) unit. 
					 PMP provides secure regions of physical memory against unauthorized access. It allows an operating system or a hypervisor to define a series of physical memory regions and then set permissions for those regions, such as read, write, and execute permissions. When a user tries to access a protected memory area (e.g., through DMA), PMP checks the access of a PMP address (e.g., pmpaddr_i) against its configuration (pmpcfg_i). If the access violates the defined permissions (e.g., CTRL_ABORT), the PMP can trigger a fault or an interrupt. This access check is implemented in the pmp parametrized module in the below code snippet. The below code assumes that the state of the pmpaddr_i and pmpcfg_i signals will not change during the different DMA states (i.e., CTRL_IDLE to CTRL_DONE) while processing a DMA request (via dma_ctrl_reg). The DMA state machine is implemented using a case statement (not shown in the code snippet).

Bad

module dma # (...)(...);
					...
						
						input [7:0] [16-1:0] pmpcfg_i;
						input logic [16-1:0][53:0]     pmpaddr_i;
						...
						//// Save the input command
  						always @ (posedge clk_i or negedge rst_ni)
							
							begin: save_inputs
							if (!rst_ni)
								
								begin
								...
								end
								
							else
								
								begin
									
									if (dma_ctrl_reg == CTRL_IDLE || dma_ctrl_reg == CTRL_DONE)
									begin
									...
									end
									
								end
								
							end // save_inputs
							...
							// Load/store PMP check
							pmp #(
								
								.XLEN       ( 64                     ),
								.PMP_LEN    ( 54                     ),
								.NR_ENTRIES ( 16           )
								
							) i_pmp_data (
								
								.addr_i        ( pmp_addr_reg        ),
								.priv_lvl_i    ( riscv::PRIV_LVL_U   ),
								.access_type_i ( pmp_access_type_reg ),
								// Configuration
								.conf_addr_i   ( pmpaddr_i           ),
								.conf_i        ( pmpcfg_i            ),
								.allow_o       ( pmp_data_allow      )
								
							);
							
						
					endmodule

Good

module dma # (...)(...);
					...
						
						input [7:0] [16-1:0] pmpcfg_i;   
						input logic [16-1:0][53:0]     pmpaddr_i;
						...
						reg [7:0] [16-1:0] pmpcfg_reg;
						reg [16-1:0][53:0] pmpaddr_reg;
						...
						//// Save the input command
						always @ (posedge clk_i or negedge rst_ni)
							
							begin: save_inputs
							if (!rst_ni)
								
								begin
								...
								pmpaddr_reg <= 'b0 ;
								pmpcfg_reg <= 'b0 ;
								end
								
							else 
								
								begin
									
									if (dma_ctrl_reg == CTRL_IDLE || dma_ctrl_reg == CTRL_DONE) 
									begin
									...
									pmpaddr_reg <= pmpaddr_i;
									pmpcfg_reg <= pmpcfg_i;
									end
									
								end 
								
							end // save_inputs
							...
							// Load/store PMP check
							pmp #(
								
								.XLEN       ( 64                     ),
								.PMP_LEN    ( 54                     ),
								.NR_ENTRIES ( 16           )
								
							) i_pmp_data (
								
								.addr_i        ( pmp_addr_reg        ),
								.priv_lvl_i    ( riscv::PRIV_LVL_U   ), // we intend to apply filter on
								// DMA always, so choose the least privilege
								.access_type_i ( pmp_access_type_reg ),
								// Configuration
								.conf_addr_i   ( pmpaddr_reg           ),
								.conf_i        ( pmpcfg_reg            ),
								.allow_o       ( pmp_data_allow      )
								
							);
							
						
					endmodule

Mitigations & Prevention

Architecture and Design

Adopting design practices that encourage designers to recognize and eliminate race conditions, such as Karnaugh maps, could result in the decrease in occurrences of race conditions.

Implementation

Logic redundancy can be implemented along security critical paths to prevent race conditions. To avoid metastability, it is a good practice in general to default to a secure state in which access is not given to untrusted agents.

Frequently Asked Questions

What is CWE-1298?

CWE-1298 (Hardware Logic Contains Race Conditions) is a software weakness identified by MITRE's Common Weakness Enumeration. It is classified as a Base-level weakness. A race condition in the hardware logic results in undermining security guarantees of the system.

How can CWE-1298 be exploited?

Attackers can exploit CWE-1298 (Hardware Logic Contains Race Conditions) to bypass protection mechanism, gain privileges or assume identity, alter execution logic. This weakness is typically introduced during the Architecture and Design, Implementation phase of software development.

How do I prevent CWE-1298?

Key mitigations include: Adopting design practices that encourage designers to recognize and eliminate race conditions, such as Karnaugh maps, could result in the decrease in occurrences of race conditions.

What is the severity of CWE-1298?

CWE-1298 is classified as a Base-level weakness (Medium abstraction). Its actual severity depends on the specific context and how the weakness manifests in your application.