CWE-1317: Improper Access Control in Fabric Bridge

Description

The product uses a fabric bridge for transactions between two Intellectual Property (IP) blocks, but the bridge does not properly perform the expected privilege, identity, or other access control checks between those IP blocks.

In hardware designs, different IP blocks are connected through interconnect-bus fabrics (e.g. AHB and OCP). Within a System on Chip (SoC), the IP block subsystems could be using different bus protocols. In such a case, the IP blocks are then linked to the central bus (and to other IP blocks) through a fabric bridge. Bridges are used as bus-interconnect-routing modules that link different protocols or separate, different segments of the overall SoC interconnect. For overall system security, it is important that the access-control privileges associated with any fabric transaction are consistently maintained and applied, even when they are routed or translated by a fabric bridge. A bridge that is connected to a fabric without security features forwards transactions to the slave without checking the privilege level of the master and results in a weakness in SoC access-control security. The same weakness occurs if a bridge does not check the hardware identity of the transaction received from the slave interface of the bridge.

Potential Impact

Demonstrative Examples

...
					module aes0_wrapper #(...)(...);
					...
						
						input logic     acct_ctrl_i;
						
					...
						
						axi_lite_interface #(...
						) axi_lite_interface_i (
						...
							
							.en_o       ( en_acct    ),
							
						
					...
					..);
						
						assign en = en_acct && acct_ctrl_i;
						
					...
					endmodule
					...
					module clint #(...)(...);
					...
						
						axi_lite_interface #(...
						) axi_lite_interface_i (
						...
							
							.en_o       ( en         ),
							
						
					...
					  );
					...
					endmodule

module clint #(...
					) (
					... 
						
						input logic     acct_ctrl_i,
						
					...
					);
						
						logic     en, en_acct;
						
					...
						
						axi_lite_interface #(...
						) axi_lite_interface_i (
						
					...
						
						.en_o       ( en_acct    ),
						
					...
						
						);
						assign en = en_acct && acct_ctrl_i;
						
					...
					endmodule

Mitigations & Prevention

Detection Methods

• Simulation / Emulation High — RTL simulation to ensure that bridge-access controls are implemented properly.
• Formal Verification High — Formal verification of bridge RTL to ensure that access control cannot be bypassed.

Real-World CVE Examples

Related Weaknesses